SK hynix Charts Co-Packaged Optics Roadmap as AI Hardware Competition Shifts to System-Level Design
Memory manufacturer SK hynix has published a technology roadmap for co-packaged optics (CPO) in the peer-reviewed journal Nature Electronics, highlighting what the company sees as the next frontier in AI hardware development.
Co-packaged optics involves integrating optical connections directly into the same package as processors and memory, rather than routing signals through discrete components on a printed circuit board. This approach addresses bandwidth and power constraints that become bottlenecks as AI training clusters scale to tens of thousands of accelerators.
The publication reflects a strategic shift in AI infrastructure competition. Rather than focusing solely on raw chip performance, industry players are increasingly designing at the system level, considering how compute, memory, and interconnects work together. SK hynix's roadmap outlines how optical I/O could enable tighter integration between high-bandwidth memory and compute dies while reducing the energy required for data movement across AI server racks.
This systems-oriented approach marks a departure from earlier generations of AI infrastructure, where improvements in GPU performance were the primary driver of capability gains. As physical limitations on transistor scaling persist, architectural innovations that optimize how chips communicate and share data are gaining prominence in research and development priorities.
The article notes that competition in the AI chip market has intensified, but the battleground is expanding from silicon to encompass packaging, interconnects, and thermal management at the rack and cluster levels.